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quad 16 - /14 - /12 - bit nano dac+ with 2 ppm/c reference, i 2 c interface data sheet ad5696r / ad5695r / ad5694r rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specif ications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2012 analog devices, inc. all rights reserved. features high relative accuracy (inl): 2 lsb maximum @ 16 bits low drift 2.5 v reference: 2 ppm/c typical tiny package: 3 mm 3 mm , 16 - lead lfcsp total unadjusted error (tue): 0.1% of fsr maximum offset error: 1.5 mv maximum gain error: 0.1% of fsr maximum high drive capability: 20 ma, 0.5 v from supply rails user selectable gain of 1 or 2 (gain pin) reset to zero scale or midscale (rstsel pin) 1.8 v logic compatibility low g litch: 0.5 nv - s ec 400 khz i 2 c - compat i ble serial interface robust 3.5 kv h bm and 1.5 kv ficdm esd rating low power: 3.3 mw at 3 v 2.7 v to 5.5 v power supply ? 40c to +105c temperature range applications optical transceivers base - station power amplifiers process control (plc i/o cards) industrial a utomation data acquisition systems functional block dia gram figure 1. general description the ad5696r / ad5695r / ad5694r family, are low power, quad, 16 - /14 - /12 - bit buffered voltage out put dacs. the devices include a 2.5 v, 2 ppm/ c internal reference (enabled by default) and a gain select pin giving a full - scale output of 2.5 v ( gain = 1) or 5 v ( gain = 2). all devices operate from a single 2.7 v to 5.5 v supply, are guaranteed monotonic by design , and exhibit less than 0.1% fsr gain error and 1.5 mv offset error performance. the devices are availabl e in a 3 mm 3 mm lfcsp and a tssop package. the ad5696r / ad5695r / ad5694r also incorporate a power - on reset circuit and a rstsel pin that ensures that the dac outputs power up to zero scale or midscale and remain there until a valid wr ite takes place. each part contains a per - channel power - down feature that reduces the current consumption of the device to 4 a at 3 v while in power - down mode. the ad5696r / ad5695r / ad5694r use a versatile 2 - wire serial interface that operates at clock rates up to 400 khz , and includes a v logic pin intended for 1.8 v/3 v/5 v logic. table 1 . quad nano dac+ devices interface reference 16 - bit 14 - bit 12 - bit spi internal ad5686r ad5685r ad5684r i 2 c internal ad5696r ad5695r ad5694r product highlights 1. high relative accuracy (inl) . ad5696r (16 - bit): 2 lsb maximum ad5695r (14 - bit): 1 lsb maximum ad5694r (12 - bit): 1 lsb maximum 2. low drift 2.5 v on - chip reference. 2 ppm/c typical temperature coefficient 5 ppm/c maximum temperature coefficient 3. two package options. 3 mm 3 mm , 16 - lead lfcsp 16- lead tssop scl v logic sda a1 a0 input register dac register string dac a buffer v out a input register dac register string dac b buffer v out b input register dac register string dac c buffer v out c input register dac register string dac d buffer v out d v ref gnd v dd 2.5v reference power- down logic power-on reset gain = 1/2 interface logic rstsel gain ldac reset ad5696r/ad5695r/ad5694r 10486-001
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteristics ........................................................................ 5 timing characteristics ................................................................ 6 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 16 theory of operation ...................................................................... 18 digital-to-analog converter .................................................... 18 transfer function ....................................................................... 18 dac architecture ....................................................................... 18 serial interface ............................................................................ 19 write and update commands .................................................. 20 serial operation ......................................................................... 21 write operation.......................................................................... 21 read operation........................................................................... 22 multiple dac readback sequence .......................................... 22 power-down operation ............................................................ 23 load dac (hardware ldac pin) ........................................... 24 ldac mask register ................................................................. 24 hardware reset ( reset ) .......................................................... 25 reset select pin (rstsel) ........................................................ 25 internal reference setup ........................................................... 25 solder heat reflow ..................................................................... 25 long-term temperature drift ................................................. 25 thermal hysteresis .................................................................... 26 applications information .............................................................. 27 microprocessor interfacing ....................................................... 27 ad5696r/ad5695r/ad5694r to adsp-bf531 interface .. 27 layout guidelines....................................................................... 27 galvanically isolated interface ................................................. 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 29 revision history 4/12revision 0: initial version
data sheet ad5696r/ad5 695r/ad5694r rev. 0 | page 3 of 32 specifications v dd = 2.7 v to 5.5 v; 1.8 v v logic 5.5 v; a ll specifications t min to t max , unless otherwise noted. r l = 2 k?; c l = 200 p f. table 2 . a grade 1 b grade 1 parameter min typ max min typ max unit test conditions/comments static performance 2 ad5696r resolution 16 16 bits relative accuracy 2 8 1 2 lsb gain = 2 2 8 1 3 gain = 1 differential nonlinearity 1 1 lsb guaranteed monotonic by design ad5695r resolution 14 14 bits relative accuracy 0.5 4 0.5 1 lsb differential nonlinearity 1 1 lsb guaranteed monotonic by design ad5694r resolution 12 12 bits relative accuracy 0.12 2 0.12 1 lsb differential nonlinearity 1 1 lsb guaranteed monotonic by design zero - code error 0. 4 4 0. 4 1.5 mv al l zeros loaded to dac register offset error + 0. 1 4 + 0. 1 1.5 mv full - scale error + 0.0 1 0.2 + 0.0 1 0.1 % of fsr all ones loaded to dac register gain error 0.02 0.2 0.02 0.1 % of fsr total unadjusted error 0.01 0.25 0.01 0.1 % of fsr external reference; g ain = 2; tssop 0.25 0.2 % of fsr internal reference ; g ain = 1; tssop offset error drift 3 1 1 v/c gain temperature coefficient 3 1 1 ppm of fsr/c dc power supply rejection ratio 3 0.15 0.15 mv/v dac code = midscale; v dd = 5 v 10 % dc crosstalk 3 2 2 v due to single channel, full - scale output change 3 3 v/ma due to load current change 2 2 v due to powering down (per chan nel) output characteristics 3 output voltage range 0 v ref 0 v ref v gain = 1 0 2 v ref 0 2 v ref v gain = 2 , see figure 31 capacitive load stability 2 2 nf r l = 10 10 nf r l = 1 k ? resistive load 4 1 1 k ? load regulation 80 80 v/ma 5 v 10%, dac code = midscale; ? 30 ma i out 30 ma 80 80 v/ma 3 v 10%, dac code = midscale; ? 20 ma i out 20 ma short - circuit curren t 5 40 40 ma load impedance at rails 6 25 25 ? see figure 31 power - up time 2.5 2.5 s coming out of power - down mode; v dd = 5 v
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 4 of 32 a grade 1 b grade 1 parameter min typ max min typ max unit test conditions/comments reference output output voltage 7 2.4975 2.5025 2.4975 2.5025 v at ambient reference tc 8 , 9 5 2 0 2 5 ppm/c see the terminology section output impedance 3 0. 0 4 0. 0 4 ? output voltage noise 3 12 12 v p - p 0.1 hz to 10 hz output voltage noise density 3 240 240 nv/hz at ambient; f = 10 khz, c l = 10 n f load regulation sourcing 3 20 20 v/ma at ambient load regulation sinking 3 40 40 v/ma at ambient output current load capability 3 5 5 ma v dd 3 v line regulation 3 1 0 0 1 0 0 v/v at ambient long - term stability / drift 3 12 12 ppm after 1000 hours at 125c thermal hysteresis 3 125 125 ppm first cycle 25 25 ppm additional cycles logic inputs 3 input current 2 2 a per pin v inl , input low voltage 0.3 v logic 0.3 v logic v v inh , input high voltage 0.7 v logic 0.7 v logic v pin capacitance 2 2 pf logic output s ( sda ) 3 output low voltage, v ol 0.4 0.4 v i sink = 3 m a floating state output capacitance 4 4 pf power requirements v logic 1.8 5.5 1.8 5.5 v i logic 3 3 a v dd 2.7 5.5 2.7 5.5 v gain = 1 v dd v ref + 1.5 5.5 v ref + 1.5 5.5 v gain = 2 i dd v ih = v dd , v il = gnd, v dd = 2.7 v to 5.5 v normal mode 10 0.59 0. 7 0. 5 9 0.7 ma internal reference off 1.1 1.3 1.1 1.3 ma internal reference on, at full scale all power - down modes 11 1 4 1 4 a ? 40c to +85c 6 6 a ? 40c to +105c 1 temperature range: a and b grade: ?40c to +105c. 2 dc specifications tested with the outputs unloaded, unless otherwise noted. upper dead band = 10 mv and exists only when v ref = v dd with gain = 1 or when v ref /2 = v dd with gain = 2. linearity calcul ated using a reduced code range of 256 to 65 , 280 ( ad5696r ), 64 to 16 , 320 ( ad5695r ) , and 12 to 4080 ( ad5694r ) . 3 guaranteed by design and characterization; not production tested. 4 channel a and channel b can have a combined output current of up to 30 ma. similarly, channel c and channel d can have a comb ined output current of up to 30 ma up to a junction temperatur e of 110c. 5 v dd = 5 v . the device includes current limiting that is intended to protect the device during tempor ary overload conditions. junction temperature can be exc e e d ed during current limit. operation above the specified max imum operation junction t emperature may impair device reliability. 6 when drawing a load current at either rail, the output voltage headroom with respect t o that rail is limited by the 25 typical channel res istance of the output devices. for example , when sinking 1 m a, the minim um output voltage = 25 ? 1 ma = 25 mv ( see figure 31 ) . 7 initial accuracy presolder reflow is 750 v; output voltage includes the effects of preconditioning drift. see the internal reference setup section. 8 reference is trimmed and tested at two temperatures and is characterized from ? 40c to +105c . 9 reference temperature coefficient calculated as per the box method. see the termino logy section for further information. 10 interface inactive. all dacs active. dac outputs unloaded. 11 all dacs powered down.
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 5 of 32 ac characteristics v dd = 2.7 v to 5.5 v; r l = 2 k? to gnd; c l = 200 pf to gnd; 1.8 v v logic 5.5 v; all specifications t min to t max , unless otherwise noted. 1 table 3 . parameter 2 min typ max unit test conditions/comments 3 output voltage settling time ad5696r 5 8 s ? to ? scale settling to 2 lsb ad5695r 5 8 s ? to ? scale settling to 2 lsb ad5694r 5 7 s ? to ? scale settling to 2 lsb slew rate 0.8 v/s digital -to - analog glitch impulse 0. 5 nv - sec 1 lsb change around major carry digital feedthrough 0.1 3 nv - sec digital crosstalk 0.1 nv - sec analog crosstalk 0.2 nv - sec dac -to - dac crosstalk 0.3 nv - s ec total harmonic distortion 4 ? 80 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz output noise spectral density 300 nv/ hz dac code = midscale, 10 khz; gain = 2 output noise 6 v p -p 0.1 hz to 10 hz snr 90 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz sfdr 83 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz sinad 80 db at ambient, bw = 20 khz, v dd = 5 v, f out = 1 khz 1 guaranteed by design and characterization; not production tested. 2 see the terminology section. 3 temperature range is ?40c to +105c, typical @ 25c. 4 digitally generated sine wave @ 1 khz.
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 6 of 32 timing characteristi cs v dd = 2.5 v to 5.5 v; 1.8 v v logic 5.5 v; all specifications t min to t max , unless otherwise noted. 1 table 4 . parameter 2 min max unit conditions/comments t 1 2.5 s scl cycle time t 2 0.6 s t high , scl high time t 3 1.3 s t low , scl low time t 4 0.6 s t hd,sta , start/repeated start condition hold time t 5 100 ns t su, dat , data setup time t 6 3 0 0.9 s t hd, dat , data hold time t 7 0.6 s t su,sta , setup time for repeated start t 8 0.6 s t su,sto , stop condition setup time t 9 1.3 s t buf , bus free time between a stop and a start condition t 10 0 300 ns t r , rise time of scl and sda when receiving t 11 20 + 0.1c b 4 300 ns t f , fall time of sda and scl when transmitting/ receiving t 12 20 ns ldac pulse width t 13 400 ns scl rising edge to ldac rising edge c b 4 400 pf capacitive load for each bus line 1 see figure 2 . 2 guaranteed by design and characterization; not production tested. 3 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih min o f the scl signal) to bridge the undefined region of scls falling edge. 4 c b is the total capacitance of one bus line in pf. t r and t f measured betwee n 0.3 v dd and 0.7 v dd . figure 2. 2 - wire serial interface timing diagram scl sda t 1 t 3 ldac 1 ldac 2 start condition repeated start condition stop condition notes 1 asynchronous ldac update mode. 2 synchronous ldac update mode. t 4 t 6 t 5 t 7 t 8 t 2 t 13 t 4 t 11 t 10 t 12 t 12 t 9 10486-002
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 7 of 32 absolute maximum ratings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v v logic to gnd ?0.3 v to +7 v v out to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd 1 ?0.3 v to v logic + 0.3 v sda and scl to gnd ?0.3 v to +7 v operating temperature range ?40c to +105c storage temperature range ?65c to +150c junction temperature 125c 16-lead tssop, ja thermal impedance, 0 airflow (4-layer board) 112.6c/w 16-lead lfcsp, ja thermal impedance, 0 airflow (4-layer board) 70c/w reflow soldering peak temperature, pb free (j-std-020) 260c esd 2 3.5 kv ficdm 1.5 kv 1 excluding sda and scl. 2 human body model (hbm) classification. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 8 of 32 pin configuration an d function descripti ons figure 3. 16 - lead lfcsp pin configuration figure 4. 16 - lead tssop pin configuration table 6 . pin function descriptions pin no. mnemonic description lfcsp tssop 1 3 v out a analog output voltage from dac a. the output amplifier has rail -to - rail operation. 2 4 gnd ground reference point for all circuitry on the part. 3 5 v dd power supply input. these parts can be operated from 2.7 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 6 v out c analog output voltage from dac c. the output amplifier has rail -to - rail operation. 5 7 v out d analog output voltage from dac d. the output amplifier has rail -to - rail operation. 6 8 sd a serial data input. this pin is used in conjunction with the scl line to clock data into or out of the 24 - bit input shift register. sda is a bidirectional, open - drain data line that should be pulled to the supply with an external pull - up resistor. 7 9 ldac ldac can be operated in two modes, asynchronously and synchronously . pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows all dac outputs to simultaneously update. this pin can also be tied permanently low . 8 10 gain span set pin. when this pin is tied to gnd , all fo ur dac outputs have a span from 0 v to v ref . if this pin is tied to v dd , all four dacs output a span of 0 v to 2 v ref . 9 11 v logic digital power supply. voltage ranges from 1.8 v to 5.5 v. 10 12 a0 address input. sets the first lsb of the 7 - bit slave address. 11 13 scl serial c lock line. this is used in conjunction with the sda line to clock data into or out of the 24 - bit input register. 12 14 a1 address input. sets the second lsb of the 7 - bit slave address. 13 15 reset asynchronous reset input. the reset input is falling edge sensitive. when reset is low, all ldac pulses are ignored. when reset is activated, the input register and the dac regis ter ar e updated with zero scale or midscale , depending on the state of the rstsel pin. 14 16 rstsel power - on reset pin. tying this pin to gnd powers up all four dacs to zero scale. tying this pin to v dd powers up all four dacs to midscale. 15 1 v ref reference voltage. the ad5696r / ad5695r / ad5694r have a common reference pin. when using the internal reference, this is the reference output pin. when using an external reference, this is the reference input pin. the default for this pin is as a reference output. 16 2 v out b analog output voltage from dac b. the output amplifier has rail -to - rail operation. 17 n/a epad exposed pad . the exposed pad must be tied to gnd. 12 11 10 1 3 4 a1 scl a0 9 v logic v out a v dd 2 gnd v out c 6 sda 5 v out d 7 ldac 8 gain 16 v out b 15 v ref 14 rstsel 13 reset ad5696r/ad5695r/ad5694r notes 1. the exposed pad must be tied to gnd. top view (not to scale) 10486-006 1 2 3 4 5 6 7 8 v out b v out a gnd v out d v out c v dd v ref sda 16 15 14 13 12 11 10 9 reset a1 scl gain ldac v logic a0 rstsel top view (not to scale) ad5696r/ ad5695r/ ad5694r 10486-007
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 9 of 32 typical performance characte risti cs figure 5. internal reference voltage vs. temperature (grade b) figure 6. internal reference voltage vs. temperature (grade a) figure 7. refer ence output temperature drift histogram figure 8. reference long - term stability/drift figure 9. internal reference noise spectral density vs. frequency figure 10 . internal reference noise , 0.1 hz to 10 hz ?40 ?20 0 20 40 60 80 100 120 v ref (v) temperature (c) device 1 device 2 device 3 device 4 device 5 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 v dd = 5v 10486-212 ?40 ?20 0 20 40 60 80 120 100 v ref (v) temperature (c) device 1 device 2 device 3 device 4 device 5 2.4980 2.4985 2.4990 2.4995 2.5000 2.5005 2.5010 2.5015 2.5020 v dd = 5v 10486-109 90 0 10 20 30 40 50 60 70 80 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 number of units temperature drift (ppm/c) v dd = 5v 10486-250 60 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 hits v ref (v) 0 hour 168 hours 500 hours 1000 hours v dd = 5.5v 10486-251 1600 0 200 400 600 800 1000 1200 1400 10 100 1k 10k 100k 1m nsd (nv/ hz) frequency (mhz) v dd = 5v t a = 25c 10486- 11 1 ch1 10v m1.0s a ch1 160mv 1 t v dd = 5v t a = 25c 10486- 1 12
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 10 of 32 figure 11 . internal reference voltage vs. load current figure 12 . internal reference voltage vs. supply voltage figure 13 . ad5696r inl figure 14 . ad5695r inl figure 15 . ad5694r inl figure 16 . ad5696r dnl 2.5000 2.4999 2.4998 2.4997 2.4996 2.4995 2.4994 2.4993 ?0.005 ?0.003 ?0.001 0.001 0.003 0.005 v ref (v) i load (a) v dd = 5v t a = 25c 10486- 1 13 2.5002 2.5000 2.4998 2.4996 2.4994 2.4992 2.4990 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v ref (v) v dd (v) d1 d3 d2 t a = 25c 10486- 1 17 10 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 0 10000 20000 30000 40000 50000 60000 inl (lsb) code v dd = 5v t a = 25c internal reference = 2.5v 10486- 1 18 10 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 0 2500 5000 7500 10000 12500 15000 16348 inl (lsb) code v dd = 5v t a = 25c internal reference = 2.5v 10486- 1 19 10 ?10 ?8 ?6 ?4 ?2 0 2 4 8 6 0 625 1250 1875 2500 3125 3750 4096 inl (lsb) code v dd = 5v t a = 25c internal reference = 2.5v 10486-120 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 0 10000 20000 30000 40000 50000 60000 dnl (lsb) code v dd = 5v t a = 25c internal reference = 2.5v 10486-121
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 11 of 32 figure 17 . ad5695r dnl figure 18 . ad5694r dnl figure 19 . inl error and dnl error vs. temperature figure 20 . inl error and dnl error vs. v ref figure 21 . inl error and dnl error vs. supply voltage figure 22 . gain error and full - scale error vs. temperature 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 0 2500 5000 7500 10000 12500 15000 16383 dnl (lsb) code v dd = 5v t a = 25c internal reference = 2.5v 10486-122 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.8 0.6 0 625 1250 1875 2500 3125 3750 4096 dnl (lsb) code v dd = 5v t a = 25c internal reference = 2.5v 10486-123 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?40 110 60 10 error (lsb) temperature (c) inl dnl v dd = 5v t a = 25c internal reference = 2.5v 10486-124 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 error (lsb) v ref (v) inl dnl v dd = 5v t a = 25c internal reference = 2.5v 10486-125 10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 2.7 5.2 4.7 4.2 3.7 3.2 error (lsb) supply voltage (v) inl dnl v dd = 5v t a = 25c internal reference = 2.5v 10486-126 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 ?40 ?20 0 20 40 60 80 100 120 error (% of fsr) temperature (c) gain error full-scale error v dd = 5v t a = 25c internal reference = 2.5v 10486-127
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 12 of 32 figure 23 . zero - code error and offset error vs. temperature figure 24 . gain error and full - scale error vs. supply figure 25 . zero - code error and offset error vs. supply figure 26 . tue v s. temperature figure 27 . tue v s. supply, gain = 1 figure 28 . tue v s. code 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 ?20 0 20 40 60 80 100 120 error (mv) temperature (c) offset error zero-code error v dd = 5v t a = 25c internal reference = 2.5v 10486-128 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 2.7 5.2 4.7 4.2 3.7 3.2 error (% of fsr) supply voltage (v) gain error full-scale error v dd = 5v t a = 25c internal reference = 2.5v 10486-129 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 2.7 5.2 4.7 4.2 3.7 3.2 error (mv) supply voltage (v) zero-code error offset error v dd = 5v t a = 25c internal reference = 2.5v 10486-130 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 ?40 ?20 0 20 40 60 80 100 120 total unadjusted error (% of fsr) temperature (c) v dd = 5v t a = 25c internal reference = 2.5v 10486-131 0.10 0.08 0.06 0.04 0.02 0 ?0.02 ?0.04 ?0.06 ?0.08 ?0.10 2.7 5.2 4.7 4.2 3.7 3.2 total unadjusted error (% of fsr) supply voltage (v) v dd = 5v t a = 25c internal reference = 2.5v 10486-132 0 ?0.01 ?0.02 ?0.03 ?0.04 ?0.05 ?0.06 ?0.07 ?0.08 ?0.09 ?0.10 0 10000 20000 30000 40000 50000 60000 65535 total unadjusted error (% of fsr) code v dd = 5v t a = 25c internal reference = 2.5v 10486-133
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 13 of 32 figure 29 . i dd histogram with external reference, 5 v figure 30 . i dd histogram with internal reference, v refout = 2.5 v , gain = 2 figure 31 . headroom/footroom vs. load current figure 32 . source and sink capability at 5 v figure 33 . source and sink capability at 3 v figure 34 . supply current vs. temperature 25 20 15 10 5 0 540 560 580 600 620 640 hits i dd (v) v dd = 5v t a = 25c external reference = 2.5v 10486-135 30 25 20 15 10 5 0 1000 1020 1040 1060 1080 1100 1120 1140 hits i dd fullscale (v) v dd = 5v t a = 25c internal reference = 2.5v 10486-136 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 0 5 10 15 20 25 30 v out (v) load current (ma) sourcing 2.7v sourcing 5v sinking 2.7v sinking 5v 10486-200 7 ?2 ?1 0 1 2 3 4 5 6 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x8000 0xc000 0x0000 v dd = 5v t a = 25c gain = 2 internal reference = 2.5v 10486-138 5 ?2 ?1 0 1 2 3 4 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 v out (v) load current (a) 0xffff 0x4000 0x8000 0xc000 0x0000 v dd = 5v t a = 25c external reference = 2.5v gain = 1 10486-139 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 ?40 110 60 10 current (ma) temperature (c) full-scale zero code external reference, full-scale 10486-140
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 14 of 32 figure 35 . settling time, 5.25 v figure 36 . power - on reset to 0 v figure 37 . exiting power - down to midscale figure 38 . digital - to- analog glitch impulse figure 39 . analog crosstalk, channel a figure 40 . 0.1 hz to 10 hz output noise plot, external reference 0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 10 320 160 40 80 20 v out (v) time (s) dac a dac b dac c dac d v dd = 5v t a = 25c internal reference = 2.5v ? to ? scale 10486-141 ?0.01 0 0.06 0.01 0.02 0.03 0.04 0.05 ?1 0 6 1 2 3 4 5 ?10 15 10 0 5 ?5 v out (v) v dd (v) time (s) ch d v dd ch a ch b ch c t a = 25c internal reference = 2.5v 10486-142 0 1 3 2 ?5 10 0 5 v out (v) time (s) ch d sync ch a ch b ch c v dd = 5v t a = 25c internal reference = 2.5v gain = 1 gain = 2 10486-143 2.4988 2.5008 2.5003 2.4998 2.4993 0 12 8 10 4 6 2 v out (v) time (s) channel b t a = 25c v dd = 5.25v internal reference code = 7fff to 8000 energy = 0.227206nv-sec 10486-144 ?0.002 ?0.001 0 0.001 0.002 0.003 0 25 20 10 15 5 v out ac-coupled (v) time (s) ch b ch c ch d 10486-145 ch1 10v m1.0s a ch1 802mv 1 t v dd = 5v t a = 25c external reference = 2.5v 10486-146
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 15 of 32 figure 41 . 0.1 hz to 10 hz output noise plot, 2.5 v internal reference figure 42 . noise spectral density figure 43 . total harmonic distortion @ 1 k hz figure 44 . settling time vs. capacitive load figure 45 . multiplying bandwidth, ext ernal ref erence = 2.5 v , 0.1 v p - p , 10 k hz to 10 mhz ch1 10v m1.0s a ch1 802mv 1 t v dd = 5v t a = 25c internal reference = 2.5v 10486-147 0 200 400 600 800 1000 1200 1400 1600 10 1m 100k 1k 10k 100 nsd (nv/ hz) frequency (hz) full-scale midscale zero-scale v dd = 5v t a = 25c internal reference = 2.5v 10486-148 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 20000 16000 8000 12000 4000 2000 18000 10000 14000 6000 thd (dbv) frequency (hz) v dd = 5v t a = 25c internal reference = 2.5v 10486-149 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 1.590 1.630 1.620 1.600 1.610 1.625 1.605 1.615 1.595 v out (v) time (ms) 0nf 0.1nf 10nf 0.22nf 4.7nf v dd = 5v t a = 25c internal reference = 2.5v 10486-150 ?60 ?50 ?40 ?30 ?20 ?10 0 10k 10m 1m 100k bandwidth (db) frequency (hz) v dd = 5v t a = 25c external reference = 2.5v, 0.1v p-p 10486-151
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 16 of 32 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot is shown in figure 13. differential nonlinearity (dnl) differential nonlinear ity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code pl ot can be seen in figure 16. zero - code error zero - code error is a measurement of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero - code error is always positive in the ad5696r because the output of the dac cannot go below 0 v due to a combination of the offset er rors in the dac and the output amplifier. zero - code error is expressed in mv. a plot of zero - code error vs. temperature can be seen in figure 23. full - scale error full - scale error is a measurement of the output error when full - scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full - scale error is expressed in percent of full - scale range (% of fsr) . a plot of full - scale error vs. temperature can be seen in figure 22. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal expressed as % of fsr. offset error drift this is a measurement of the change in offset error with a change in temperature. it is expressed in v/c. gain temperature coefficient this is a measurement of the c hange in gain error with changes in temperature. it is expressed in ppm of fsr/c. offset error offset error is a measure of the difference between v out (actual) and v out (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the ad5696r with code 512 loaded in the dac register. it can be negative or positive. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full - scale output of the dac. it is measured in mv/v . v ref is held at 2 v, and v dd is varied by 10%. output voltage settling time this is the amount of time it takes for the output of a dac to settle to a specified level for a ? to ? full - scale input ch ange . digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv - s ec , and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000) (see figure 38). digital feedthrough digital feedthr ough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output i s not updated. it is specified in nv - s ec , and measured with a full - scale code change on the data bus, that is, from all 0s to all 1s and vice versa. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output t o the reference input when the dac output is not being updated. it is expressed in db. noise spectral density this is a measurement of the internally generated random noise. random noise is characterized as a spectral density (nv/hz). it is measured by l oading the dac to midscale and measuring noise at the output. it is measured in nv/hz. a plot of noise spectral density is shown in figure 42. dc crosstalk dc crossta lk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on one dac (or soft power - down and power - up) while monitoring another dac kept at midscale. it is expres sed in v. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in v/ma. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full - scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nv - s ec .
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 17 of 32 analo g crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full - scale code change (all 0s to all 1s and vice versa). then execute a s oftware ldac and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in nv - s ec . dac -to - dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequ ent analog output change of another dac. it is measured by loading the attack channel with a full - scale code change (all 0s to all 1s and vice versa) , using the write to and update command s while monitor - ing the output of the victim channel that is at mids cale. the energy of the glitch is expressed in nv - s ec . multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full - scale code loaded to the dac) appear s on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) this is the difference between an ideal sine wave and its attenuated version using the dac. the sine w ave is used as the reference for the dac, and the thd is a measurement of the harmonics present on the dac output. it is measured in db. voltage reference tc voltage reference tc is a measure of the change in the reference output voltage with a change in t emperature. the reference tc is calculated using the box method, which defines the tc as the maximum change in the reference output over a given tempera - ture range expressed in ppm/c as follows; 6 10 ? ? ? ? ? ? ? ? ? = temprange v v v tc refnom refmin refmax where: v refmax is the maximum reference output measured over the total temperature range. v refmin is the minimum reference output measured over the total temperature range. v refnom is the nominal reference output voltage, 2.5 v. temprange is the specified temperature ra nge of ? 40c to +10 5c.
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 18 of 32 theory of operation digital - to - analog converter t he ad5696r / ad5695r / ad5694r are quad 1 6 - /14 - /12 - bit, serial input, voltage output dacs with an internal reference. the parts operate from supply voltages of 2.7 v to 5.5 v. data is written to the ad5696r / ad5695r / ad5694r in a 2 4 - bit word format via a 2 - wire serial interface. th e ad5696r / ad5695r / ad5694 r incorporate a power - on reset circuit to ensure that the dac output powers up to a known output state. the devices also have a software power - down mode that reduces the typical current consumption to typically 4 a . transfer function the internal reference is on by default. to use an external reference , only a nonreference option is available. because the input coding to the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n ref out d gain v v 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register as follows: 0 to 4,095 for the 12 - bit device. 0 to 16,383 for the 14 - bit device. 0 to 65,535 for the 16 - bit device . n is the dac resolution. gain is the gain of the output amplifier and is set to 1 by default. this can be set to 1 or 2 using the g ain select pin . when this pin is tied to gnd, all four dac outputs have a span from 0 v to v ref . if this pin is tied to v dd , all four dacs output a span of 0 v to 2 v ref . dac architecture the dac architecture consists of a string dac followed by an output amplifier. figure 46 shows a block diagram of the dac ar c hitecture. figure 46 . single dac channel architecture block diagram the resistor string structure is shown in figure 47 . it is a string of resistors, each of value r. the code loaded to the dac register determines the node on the string where the voltage is to be tapped off and fed into the output amplifier. t he voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. figure 47 . resistor string structure internal reference the ad5696r / ad5695r / ad5694r on - chip reference is on at power - up but can be disabled via a write to a control register. see the internal reference setup section for details. the ad5696r / ad5695r / ad5694r ha ve a 2.5 v, 2 ppm/c reference , giving a full - scale output of 2.5 v or 5 v depending on the state of the gain pin. the internal reference associated with the device is available at the v ref pin. this buffe r ed reference is capable of driving external loads of up to 10 ma . output amplifiers the output buffer amplifier can generate rail - to - rail voltages on its output, which gives an output range of 0 v to v dd . the actual range depends on the value of v ref , the gain pin, offset error , and gain error. the gain pin selects the gain of the output . ? if this pin is tied to gnd , all four output s have a gain of 1 and the output range is 0 v to v ref . ? if this pin is tied to v logic , all four output s have a gain of 2 and the output range is 0 v to 2 v ref . these amplifiers are capable of driving a load o f 1 k? in parallel with 2 n f to gnd. the slew rate is 0.8 v/s with a ? to ? scale settling time of 5 s. input register 2.5v ref dac register resistor string ref (+) v ref gnd ref (?) v out x gain (gain = 1 or 2) 10486-052 r r r r r to output amplifier v ref 10486-053
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 19 of 32 serial interface t he ad5696r / ad5695r / ad5694r have 2 - wire i 2 c - compatible serial interfaces (refer to i 2 c - bus specification , version 2.1, january 2000, available from philips semiconductor) . see figure 2 for a timing diagram of a typi cal write sequence. the ad5696r / ad5695r / ad5694r can be connected to an i 2 c bus as a slave device, under the control of a master device . the ad5696r / ad5695r / ad5694r support sta ndard (100 khz) and fast (400 khz) data transfer modes. support is not provided for 10 - bit addressing and general call addressing. input shift register the input shift register of the ad5696r / ad5695r / ad5694r is 2 4 bits wide. data is loaded into the device as a 24 - bit w ord under the control of a serial clock input, scl. the first eight msbs make up the command byte. the first four bits are the command bits (c3, c2, c1, c0) that control the mode of operation of the device (s ee table 7 ) . the last 4 bits of first byte are the address bits ( dac a, dac b, dac c, dac d ) (s ee table 8 ). the d ata - word comprises 1 6 - bit, 14 - bit, or 1 2 - b it input code, followed by four , two, or zero dont care bits for the ad5696r , ad5695r , and ad5694r , respectively (see figure 48, figure 49, and figure 50 ). these data bits are transfe rr ed to the input register on the 24 falling edges of scl . comm ands can be executed on individual dac channels, combined dac channels , or on all dacs , depending on the address bits selected . table 7 . command definitions command c3 c2 c1 c0 description 0 0 0 0 no operation 0 0 0 1 write to input register n (d ependent on ldac ) 0 0 1 0 update dac register n with contents of input register n 0 0 1 1 wr ite to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 hardware ldac mask register 0 1 1 0 software r eset (power - on reset) 0 1 1 1 internal r eference setup register 1 0 0 0 reserved reserved 1 1 1 1 reserved table 8 . address commands address (n) selected dac channel 1 dac d dac c dac b dac a 0 0 0 1 dac a 0 0 1 0 dac b 0 1 0 0 dac c 1 0 0 0 dac d 0 0 1 1 dac a and dac b 1 1 1 1 1 all dacs 1 any combination of dac channels can be selected using the address bits. figure 48 . ad5696r input shift register content figure 49 . ad5695r input shift register content figure 50 . ad5694r input shift register content db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 dac d dac c dac b dac a d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x command dac address dac data dac data command byte data high byte data low byte 10486-300 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 dac d dac c dac b dac a d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x command dac address dac data dac data command byte data high byte data low byte 10486-301 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c3 c2 c1 c0 dac d dac c dac b dac a d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command dac address dac data dac data command byte data high byte data low byte 10486-302
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 20 of 32 w rite and update comm ands write to input register n (dependent on ldac ) command 0001 allows the user to write to each dac s dedicated input register individually. when ldac is low , the input register is transparent (if not controlled by the ldac mask register). update dac register n with contents of input register n command 0010 loads the dac registers/outputs with the contents of the input registers selected and update s the dac outputs directly. write to and update dac channel n (independent of ldac ) command 0011 allows the user to write to the dac registers and update the dac outputs directly.
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 21 of 32 s erial operation the ad5696r / ad5695r / ad5694r each have a 7 - bit slave address. the five msbs are 00011 and the two lsbs (a1, a0) are set by the state of the a0 and a1 address pin s . the ability to make hardwired changes to a0 and a1 allows the user to incorpor ate up to four of these devices on one bus, as outlined in table 9 . table 9 . device address selection a0 pin connection a1 pin connection a0 a1 gnd gnd 0 0 v logic gnd 1 0 gnd v logic 0 1 v logic v logic 1 1 the 2 - wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition when a high - to - low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7 - bit slave address. the slave address corresponding to the transmitted address responds by pulling sda low during the 9 th clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bi t). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the 9 th clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse, and then high du ring the 10 th clock pulse to establish a stop condition. write operation when writing to the ad5696r / ad5695r / ad5694r , the user must begin with a start command followed by an address byte ( r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. the ad5696r / ad5695r / ad5694r require two bytes of data for the dac and a command byte that controls various dac functions. three bytes of data must , th erefore , be written to the dac with the command byte followed by the most significant data byte and the least significant data byte, as shown in figure 51 . all these data bytes are acknowledged by the ad5696r / ad5695r / ad5694r . a stop condition follows. figure 51 . i 2 c write operation frame 2 command byte frame 1 slave address 1 9 9 1 scl start by master ack. by ad56x6 ack. by ad56x6 sda r/w db23 a0 a1 1 0 0 0 1 db22 db21 db20 db19 db18 db17 db16 1 9 9 1 ack. by ad56x6 ack. by ad56x6 frame 4 least significant data byte frame 3 most significant data byte stop by master scl (continued) sda (continued) db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 10486-303
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 22 of 32 r ead o peration when reading data back from the ad5696r dacs, the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. this address byte must be followed by the control byte that determines both the read command that is to follow and the pointer address to read from, which is al so ackn owledged by the dac. the user configures which channel to read back and sets the readback command to active using the control byte. following this, there is a repeated start condition by the master and the address is resent with r/ w = 1. this is acknowledged by the dac , indicating that it is prepared to transmit data. two bytes of data are then read fro m the dac, as shown in figure 52 . a nack condition from the master , followed by a stop condition , completes the read sequence. default readback is channel a if more than one dac is selected. m ultiple dac readback sequence the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. this address byte must be followed by the control byte, which is also acknowledged by the dac. the user configures which channel to start the readback using the control byte . following this, there is a repeated start condition by the master and the address is resent with r/ w = 1. this is acknowledged by the dac , indicating that it is prepared to transmit data. the first two bytes of data are then read from t he dac input register n select ed using the control byte, most significant byte first as shown in figure 52 . the next two bytes read back are the contents of dac input register n + 1 , the next bytes read back are the contents of dac input register n + 2. data continue s to be read from the dac input registers in this auto - incremental fashion, until a nack followed by a stop condition follows. if the contents of dac input register d are read out , the next two bytes of data that are read are from the contents of dac input register a. figure 52 . i 2 c read operation frame 2 command byte frame 1 slave address 1 1 0 0 0 1 a1 a0 r/w db23 db22 db21 db20 db19 db18 db17 db16 9 9 1 start by master ack. by ad5696r ack. by ad5696r scl scl sda 1 9 9 1 1 9 9 1 ack. by ad5696r repeated start by master ack. by ad5696r frame 4 most significant data byte n frame 3 slave address ack. by master nack. by ad5696r stop by master frame 4 most significant data byte n ? 1 frame 3 slave address significant data byte n 1 0 0 0 1 a1 a0 r/w db15 db14 db13 db12 db11 db10 db9 db8 sda scl (continued) sda (continued) db7 db6 db5 db4 db3 db2 db1 db0 db15 db14 db13 db12 db11 db10 db9 db8 10486-304
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 23 of 32 power - down operation the ad5696r / ad5695r / ad5694r contain three separate power - down mode s. command 0100 is designated for the power - down function (see table 7 ). t hese power - down modes are software - programmable by setting eight bits, bit db7 to bit db0 , in the shift register. there are two bits associated with each dac channel. table 10 shows how the state of the two bits corresponds to the mode of operation of the device. table 10 . modes of operation operating mode pdx1 pdx0 normal operation 0 0 power - down modes 1 k ? to gnd 0 1 100 k ? to gnd 1 0 three - state 1 1 any or all dacs (dac a to dac d ) can be powered down to the selected mode by setting th e corresponding bits . see table 11 for the contents of the input shift register during the power - down/power - up operation. when both bit pd x 1 and bit pd x 0 (where x is the channel selected) in the input shift register are set to 0, the part s work normally with its normal power consumption of 4 ma at 5 v. however, for th e three power - down modes, the supply current falls to 4 a at 5 v. not only does the supply current fall, but the output stage is also internally switch ed from the output of the amplifier to a resistor network of known values . this has the advantage that the output impedance of the part is known while the part is in power - down mode. there are three different power - down options. the output is connected int er nally to gnd through either a 1 k? or a 100 k? resistor, or it is left open - circuited (three - state). the output stage is illustrated in figure 53. figure 53 . output stage during power - down the bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when the power - down mode is activated. however, the contents of the dac register are unaffe cted when in power - down. the dac register can be updated while the device is in power - down mode. the time required to exit power - down is typically 4.5 s for v dd = 5 v . to reduce the current consumption further , the on - chip reference can be powered off. se e the internal reference setup section. table 11 . 24- bit input shift register contents of power - down/power - up operation 1 db23 db22 db21 db20 db19 to db16 db15 to db8 db7 db6 db5 db4 db3 db2 db1 db0 (lsb) 0 1 0 0 x x pdd1 pdd0 pdc1 pdc0 pdb1 pdb0 pda1 pda0 command bits (c3 to c0) address bits dont care power - down select dac d power - down select dac c power - down select dac b power - down select dac a 1 x = dont care. resistor network v out x dac power-down circuitry amplifier 10486-058
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 24 of 32 load dac (hardware ldac pin) the ad5696r / ad5695r / ad5694r dacs have double buffered interfaces consisting of two banks of registers: input registers and dac registers. the user can write to any combination of the input registers. updates to the dac register are controlled by the ldac pin. figure 54. simplified diagram of input loading circuitry for a single dac instantaneous dac updating ( ldac held low) ldac is held low while data is clocked into the input register using command 0001. both the addressed input register and the dac register are updated on the 24 th clock and the output begins to change (see table 13). deferred dac updating ( ldac is pulsed low) ldac is held high while data is clocked into the input register using command 0001. all dac outputs are asynchronously updated by taking ldac low after the 24 th clock. the update now occurs on the falling edge of ldac . ldac mask register command 0101 is reserved for this software ldac function. address bits are ignored. writing to the dac, using command 0101, loads the 4-bit ldac register (db3 to db0). the default for each channel is 0; that is, the ldac pin works normally. setting the bits to 1 forces this dac channel to ignore transitions on the ldac pin, regardless of the state of the hardware ldac pin. this flexibility is useful in applications where the user wishes to select which channels respond to the ldac pin. table 12. ldac overwrite definition load ldac register ldac bits (db3 to db0) ldac pin ldac operation 0 1 or 0 determined by the ldac pin. 1 x 1 dac channels update and override the ldac pin. dac channels see ldac as 1. 1 x = dont care. the ldac register gives the user extra flexibility and control over the hardware ldac pin (see table 12). setting the ldac bits (db0 to db3) to 0 for a dac channel means that this channels update is controlled by the hardware ldac pin. table 13. write commands and ldac pin truth table 1 commands description hardware ldac pin state input register contents dac register contents 0001 write to input register n (dependent on ldac ) v logic data update no change (no update) gnd 2 data update data update 0010 update dac register n with contents of input register n v logic no change updated with input register contents gnd no change updated with input register contents 0011 write to and update dac channel n v logic data update data update gnd data update data update 1 a high to low hardware ldac pin transition always updates the contents of the contents of the dac register with the contents of the input register on chan nels that are not masked (blocked) by the ldac mask register. 2 when ldac is permanently tied lo w, the ldac mask bits are ignored. sdo scl v out dac register input shift register output amplifier ldac refin input register 12-/14-/16-bit dac 10486-059
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 25 of 32 hardware reset ( reset ) reset is an active low reset that allows the outputs to be cleared to either zero scale or midscale. the clear code value is user selectable via the reset select pin. it is necessary to keep reset low for a minimum amount of time to complete the operation (see figure 2). when the reset signal is returned high, the output remains at the cleared value until a new value is programmed. the outputs cannot be updated with a new value while the reset pin is low. there is also a software executable reset function that resets the dac to the power-on reset code. command 0110 is designated for this software reset function (see table 7). any events on ldac or reset during power-on reset are ignored. reset select pin (rstsel) the ad5696r / ad5695r / ad5694r contain a power-on reset circuit that controls the output voltage during power-up. by connecting the rstsel pin low, the output powers up to zero scale. note that this is outside the linear region of the dac; by connecting the rstsel pin high, v out powers up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. internal reference setup the on-chip reference is on at power-up by default. to reduce the supply current, this reference can be turned off by setting software programmable bit, db0, in the control register. table 14 shows how the state of the bit corresponds to the mode of operation. command 0111 is reserved for setting up the internal reference (see figure 6). table 14 shows how the state of the bits in the input shift register corresponds to the mode of operation of the device during internal reference setup. table 14. reference setup register internal reference setup register (db0) action 0 reference on (default) 1 reference off solder heat reflow as with all ic reference voltage circuits, the reference value experiences a shift induced by the soldering process. analog devices, inc., performs a reliability test called precondition to mimic the effect of soldering a device to a board. the output voltage specification quoted previously includes the effect of this reliability test. figure 55 shows the effect of solder heat reflow (shr) as measured through the reliability test (precondition). figure 55. shr reference voltage shift long-term temperature drift figure 56 shows the change in v ref value after 1000 hours in life test at 150c. figure 56. reference drift through to 1000 hours 60 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 hits v ref (v) postsolder heat reflow presolder heat reflow 10486-060 60 0 10 20 30 40 50 2.498 2.499 2.500 2.501 2.502 hits v ref (v) 0 hour 168 hours 500 hours 1000 hours 10486-061
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 26 of 32 thermal hysteresis thermal hysteresis is the voltage difference induced on the reference voltage by sweeping the temperature from ambient to cold, to hot and then back to ambient. thermal hysteresis data is shown in figure 57. it is measured by sweeping temperature from ambient to ?40 c, then to +105 c, and returning to ambient. the v ref delta is then measured between the two ambient measurements and shown in blue in figure 57. the same temperature sweep and measurements were immediately repeated and the results are shown in red in figure 57. figure 57. thermal hysteresis table 15. 24-bit input shift register contents for internal reference setup command 1 db23 (msb) db22 db21 db20 db 19 db18 db17 db16 db15 to db1 db0 (lsb) 0 1 1 1 x x x x x 1/0 command bits (c3 to c0) address bits (a2 to a0) dont care reference setup register 1 x = dont care. 9 8 7 6 5 4 3 2 1 0 50 0 ?50 ?100 ?150 ?200 hits distortion (ppm) first temperature sweep subsequent temperature sweeps 10486-062
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 27 of 32 applications information microprocessor interfacing microprocessor interfacing to the ad5696r / ad5695r / ad5694r is via a serial bus that uses a standard protocol that is compatible with dsp processors and microcontrollers. the communications channel requires a 2-wire interface consisting of a clock signal and a data signal. ad5696r/ad5695r/ad5694r to adsp-bf531 interface the i 2 c interface of the ad5696r / ad5695r / ad5694r is designed to be easily connected to industry-standard dsps and microcontrollers. figure 58 shows the ad5696r / ad5695r / ad5694r connected to the analog devices blackfin? dsp. the blackfin has an integrated i 2 c port that can be connected directly to the i 2 c pins of the ad5696r / ad5695r / ad5694r . figure 58. adsp-bf531 interface layout guidelines in any circuit where accuracy is important, careful consider- ation of the power supply and ground return layout helps to ensure the rated performance. the pcb on which the ad5696r / ad5695r / ad5694r are mounted should be designed so that the ad5696r / ad5695r / ad5694r lie on the analog plane. the ad5696r / ad5695r / ad5694r should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply, located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. in systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. the ad5696r / ad5695r / ad5694r lfcsp models have an exposed paddle beneath the device. connect this paddle to the gnd supply for the part. for optimum performance, use special considerations to design the motherboard and to mount the package. for enhanced thermal, electrical, and board level performance, solder the exposed paddle on the bottom of the package to the corresponding thermal land paddle on the pcb. design thermal vias into the pcb land paddle area to further improve heat dissipation. the gnd plane on the device can be increased (as shown in figure 59) to provide a natural heat sinking effect. figure 59. paddle connection to board galvanically isolated interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. i coupler? products from analog devices provide voltage isolation in excess of 2.5 kv. the serial loading struc- ture of the ad5696r / ad5695r / ad5694r makes the part ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 60 shows a 4-channel isolated interface to the ad5696r / ad5695r / ad5694r using an adum1400 . for further information, visit http://www.analog.com/icouplers . figure 60. isolated interface adsp-bf531 scl gpio1 sda gpio2 ldac pf9 reset pf8 ad5696r/ ad5695r/ ad5694r 10486-164 ad5696r/ ad5695r/ ad5694r gnd plane board 10486-166 encode serial clock in controller adum1400 1 serial data out reset out load dac out decode to scl to sda to reset to ldac v ia v oa encode decode v ib v ob encode decode v ic v oc encode decode v id v od 1 additional pins omitted for clarity. 10486-167
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 28 of 32 outline dimensions figure 61 . 16 - lead lead frame chip scale package [lfcsp _wq ] 3 mm 3 mm body, very very thin quad (cp - 16 - 22 ) dimensions shown in millimeters figure 62 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters 3.10 3.00 sq 2.90 0.30 0.23 0.18 1.75 1.60 sq 1.45 08-16-2010-e 1 0.50 bsc bot t om view top view 16 5 8 9 12 13 4 exposed pa d pin 1 indic a t or 0.50 0.40 0.30 sea ting plane 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 29 of 32 ordering guide model 1 resolution temperature range accuracy reference t empco (ppm/c) package description package option branding ad5696r acpz -rl7 16 bits ? 40c to +105c 8 lsb inl 5 (typ) 16 - lead lfcsp_w q cp -16 -2 2 dja ad5696r bcpz - rl7 16 bits ? 40c to +105c 2 lsb inl 5 (max) 16 - lead lfcsp_wq cp -16 -22 djd ad5696r aruz 16 bits ? 40c to +105c 8 lsb inl 5 (typ) 16 - lead tssop ru -16 ad5696r aruz -rl7 16 bits ? 40c to +105c 8 lsb inl 5 (typ) 16 - lead tssop ru -16 ad5696r bruz 16 bits ? 40c to +105c 2 lsb inl 5 (max) 16 - lead tssop ru -16 ad5696r bruz -rl7 16 bits ? 40c to +105c 2 lsb inl 5 (max) 16 - lead tssop ru -16 ad5695r bcpz - rl7 14 bits ? 40c to +105c 1 lsb inl 5 (max) 16 - lead lfcsp_wq cp -16 -22 djr ad5695r aruz 14 bits ? 40c to +105c 4 lsb inl 5 (typ) 16 - lead tssop ru -16 ad5695r aruz -rl7 14 bits ? 40c to +105c 4 lsb inl 5 (typ) 16 - lead tssop ru -16 ad5695r bruz 14 bits ? 40c to +105c 1 lsb inl 5 (max) 16 - lead tssop ru -16 ad5695r bruz -rl7 14 bits ? 40c to +105c 1 lsb inl 5 (max) 16 - lead tssop ru -16 ad5694r bcpz - rl7 12 bits ? 40c to +105c 1 lsb inl 5 (max) 16 - lead lfcsp_wq cp -16 -22 djl ad5694r aruz 12 bits ? 40c to +105c 2 lsb inl 5 (typ) 16 - lead tssop ru -16 ad5694r aruz - rl7 12 bits ? 40c to +105c 2 lsb inl 5 (typ) 16 - lead tssop ru - 16 ad5694r bruz 12 bits ? 40c to +105c 1 lsb inl 5 (max) 16 - lead tssop ru - 16 ad5694r bruz -rl7 12 bits ? 40c to +105c 1 lsb inl 5 (max) 16 - lead tssop ru -16 eval - ad5696r sdz ad5696r tssop evaluation board eval - ad5694r sdz ad5694r tssop evaluation board 1 z = rohs compliant part.
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 30 of 32 notes
data sheet ad5696r/ad5695r/ad5694r rev. 0 | page 31 of 32 notes
ad5696r/ad5695r/ad5694r data sheet rev. 0 | page 32 of 32 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10486 - 0 - 4/12(0)

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